1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor device including a delay device.
2. Description of the Prior Art
A semiconductor device loaded with a delay device has been widely used. In the semiconductor device, a delay time of the delay device can perform an important function in the operations of the semiconductor device. Therefore, to guarantee the functions of the semiconductor device, it is necessary to test the delay time of the delay device. Conventionally, in this case, a measuring device for measuring the delay time externally for the semiconductor device is connected to the delay device to measure the delay time.
FIG. 9 shows the configuration of a conventional semiconductor device 100 loaded with a delay device and the configuration of a measuring device 200 for measuring the delay time of the delay device. The conventional semiconductor device 100 includes an internal circuit 101, a multiplexer 102, a delay device 103, an input buffer 104, and an output buffer 105. The input buffer 104 is used to input a signal into the semiconductor device 100 from a device external to the semiconductor device 100. The output buffer 105 is used to output a signal from the semiconductor device 100 to a device external to the semiconductor device 100.
The internal circuit 101 is connected to the first input line of the multiplexer 102. The second input line of the multiplexer 102 is connected to the output line of the input buffer 104. The multiplexer 102 selectively connects either internal circuit 101 or input buffer 104 to the delay device 103. The delay device 103 is connected to the input lines of the internal circuit 101 and the output buffer 105.
The measuring device 200 includes a control circuit 201, a trigger pulse generation circuit 202, and a delay time identification circuit 203. The control circuit 201 controls the entire measuring device 200. The trigger pulse generation circuit 202 inputs a test input signal TIN into the semiconductor device 100. The delay time identification circuit 203 identifies a delay time of the delay device 103 loaded into the semiconductor device 100 from the test output signal TOUT output from the semiconductor device 100.
When the semiconductor device 100 operates normal operations, the multiplexer 102 connects the delay device 103 to the internal circuit 101. The internal circuit 101 inputs an input signal IN into the delay device 103 through the multiplexer 102. The delay device 103 generates an output signal OUT by delaying the input signal IN, and outputs it to the internal circuit 101.
When the delay time of the delay device 103 is measured, the measuring device 200 is connected to the semiconductor device 100. Then, the multiplexer 102 connects the delay device 103 to the input buffer 104.
The test input signal TIN that is output by a trigger pulse generation circuit 202 is input into the delay device 103 through the input buffer 104 and the multiplexer 102. The delay device 103 outputs the test output signal TOUT by delaying the test input signal TIN. The test output signal TOUT is output to the delay time identification circuit 203 through the output buffer 105. The time xcfx84 required from the input of the test input signal TIN into the semiconductor device 100 to the output of the test output signal TOUT from the semiconductor device 100 is obtained by adding up the delay times of the input buffer 104, the multiplexer 102, the delay device 103, and the output buffer 105. The delay time identification circuit 203 identifies the delay time of the delay device 103 by subtracting the delay times occurring in the input buffer 104 and the output buffer 105 from the required time xcfx84.
However, it is not desired to input the test input signal TIN into the delay device 103 through the input buffer 104 with a view to improving the measurement precision of the delay time of the delay device 103. Similarly, it is not desired to output the test output signal TOUT from the delay device 103 through the output buffer 105 with a view to improving the measurement precision of the delay time of the delay device 103. The main reasons are described below.
The input buffer 104 and the output buffer 105 connected to devices external to the semiconductor device cannot be reduced in size to protect the semiconductor device against the electrostatic destruction by static electricity which can be externally applied. Therefore, the delay times occurring in the input buffer 104 and the output buffer 105 are necessarily long to a certain extent. To be more practical, the delay times occurring in the input buffer 104 and the output buffer 105 are normally longer than 1 ns. Since the delay times occurring in the input buffer 104 and the output buffer 105 depend on various production conditions, it is difficult to make the measurement error of the delay time of the delay device 103 smaller than the delay times occurring in the input buffer 104 and the output buffer 105.
It is desired that the delay time of the delay device loaded into the semiconductor device is more correctly measured.
Object of the Invention
The present invention aims at providing a semiconductor device which is loaded with a delay device and is capable of more correctly measuring the delay time of the delay device.
Summary of the Invention
The semiconductor device according to the present invention is provided with a semiconductor chip including a delay unit having a delay time and a delay time measuring unit for measuring a delay time. The delay time measuring unit generates a measurement result signal, that is, a digital signal, based on the delay time, and outputs the measurement result signal outside the semiconductor chip.